ÄÄÇ»ÅÍ > RAM > DDR
»ï¼º DDR 1G PC-3200¢â
DDR400 / 1GB / 184pin / CL 3
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Ãâ½ÃÀÏÀÚ : 2005/04
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Á¦Ç°Á¦°øÃ³ : µðÁö¿÷½ºÄÚ¸®¾Æ 02-715-7787
»ï¼º DDR 1G PC-3200¢â
DDR400 / 1GB / 184pin / CL 3

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ÄÁÅÙÃ÷Á¦ÀÛ»ç : (ÁÖ)µðºñ³ª¿Í
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Samsung 1GB DDR SDRAM PC3200 Á¦Ç°Àº 184ÇÉ unbuffered DIMM ¼ÒÄÏ ±Ô°ÝÀÇ ¾ç¸é ¸Þ¸ð¸®ÀÔ´Ï´Ù. 1GBÀÇ ¿ë·®À» °¡Áö°í ÀÖÀ¸¸ç PC3200 SDRAM module Á¦Ç°À¸·Î 400MhzÀÇ Å¬·° ½ºÇǵå·Î µ¿À۵˴ϴÙ.
 

ºÎÂøµÈ ½ºÆ¼Ä¿¸¦ Á¦°Å½Ã A/S¿¡ ºÒÀÌÀÍÀÌ ¹ß»ýÇϹǷΠÀ¯ÀÇ ÇϽñ⠹ٶø´Ï´Ù.
 

DDR400 À¸·Î µ¿ÀÛÇϰí CL 3ÀÇ ·¹ÀÌÅϽø¦ °¡Áø Á¦Ç°ÀÔ´Ï´Ù.

* ¸Þ¸ð¸®ÀÇ ½ºÆåÀº ÇØ´ç ¸ðµâ³Ñ¹öÀÇ º¯°æ¿¡ ÀÇÇØ º¯°æµÉ ¼ö ÀÖ½À´Ï´Ù.
 

  • VDD : 2.5V ¡¾ 0.2V, VDDQ : 2.5V ¡¾ 0.2V for DDR 266, 333
  • VDD : 2.6V ¡¾ 0.1V, VDDQ : 2.6V ¡¾ 0.1V for DDR 400
  • Double-data-rate architecture; two data transfers per clock cycle
  • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
  • Four banks operation
  • Differential clock inputs(CK and /CK)
  • DLL aligns DQ and DQS transition with CK transition
  • MRS cycle with address key programs
  • - Read latency : DDR 266(2, 2.5 Clock), DDR 333(2.5 Clock), DDR 400(3 Clock)
    - Burst length (2, 4, 8)
    - Burst type (sequential & interleave)
  • All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
  • Data I/O transactions on both edges of data strobe
  • Edge aligned data output, center aligned data input
  • LDM, UDM for write masking only (x16)
  • DM for write masking only (x4, x8)
  • Auto & Self refresh
  • 7.8¥ìs refresh interval(8K/64ms refresh)
  • Maximum burst refresh cycle : 8
  • 66pin TSOP II & 60Ball FBGA Pb-Free package(RoHS compliant)
     

 
º» ÀÚ·áÀÇ ÀúÀÛ±ÇÀº (ÁÖ)µðºñ³ª¿Í¿¡ ÀÖÀ¸¸ç µ¿ÀǾøÀÌ ¹«´Üº¹Á¦ ¹× °¡°ø, ÀÓÀÇ·Î »ç¿ë½Ã
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»óǰ Á¤º¸·Î Á¦Á¶»ç »çÁ¤¿¡ µû¶ó º¯°æµÉ ¼ö ÀÖÀ¸¸ç ÀÌ¿¡ ´ëÇÏ¿© ´ç»ç´Â Ã¥ÀÓÁöÁö ¾Ê½À´Ï´Ù.
* ÃÖÁ¾¼öÁ¤ÀÏ : 2005-04-04
* ÀúÀ۱ǹýó¹ú * ÀúÀ۱Ǿȳ» {ÄÜÅÙÃ÷Á¤º¸Á¦ÀÛ ¢ßµðºñ³ª¿Í}

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